AMD kicked off its annual Advancing AI conference in San Francisco this week with the commercial debut of its next-generation EPYC Venice processor, a 256-core server CPU built on TSMC’s 2nm process that promises a 70% compute uplift over the previous Turin generation.
The Zen 6-based Venice chip, paired with AMD’s new Instinct MI400 accelerator family offering up to 432 GB of HBM4 memory, forms the backbone of the company’s Helios rack-scale AI systems. Each Venice socket delivers 1.6 TB/s of memory bandwidth over 16 DDR5 channels and supports PCIe Gen 6, doubling CPU-to-GPU bandwidth for accelerator-heavy workloads.
The MI400 accelerators bring 19.6 TB/s of memory bandwidth and 40 PFLOPs of FP4 compute, positioning them against NVIDIA’s next-generation offerings in the training and inference market.
The announcements come as AMD’s data center business accelerates. The company captured a record 46.2% of x86 server CPU revenue in the first quarter of 2026, with data center revenue hitting $5.78B, up 57% year over year.
CEO Lisa Su’s keynote on Thursday is expected to include additional ecosystem partnerships and customer commitments, with Microsoft and other cloud providers already bringing Venice platforms online.
