Samsung introduced a new generation of AI memory at the Future of Memory and Storage conference in Santa Clara on Tuesday, headlined by a prototype NAND chip with more than 400 layers.
The V10 Bonding V-NAND, or BV-NAND, uses a wafer-bonding architecture that Samsung says lifts density by about 58% over its V9 NAND while improving read, write and input/output performance. The company framed the shift as a response to AI workloads that now stretch from training large models to generating answers for user queries, where high-capacity and power-efficient storage are in demand.
Samsung also showed concept models of what it called the industry’s first zHBM and zNAND-O architectures. Unlike conventional high-bandwidth memory placed beside AI processors, zHBM stacks memory vertically above accelerators, shortening the distance data travels to raise bandwidth and cut energy use. Samsung says the wafer-bonding technology could enable more than ten times the memory density of HBM5 while tripling energy efficiency and cutting thermal resistance by more than half.
The announcement follows Samsung’s disclosure last week that long-term agreements with customers could eventually account for 60% to 70% of its memory sales, with analysts pointing to exceptionally strong AI demand.
